Lunimav0.19.0
Lunima

Open-source photonic IC design  ·  λ = 1550 nm

Draw the chip.
Watch the light.

Lunima is a free, open-source design tool for photonic integrated circuits. Place parts, let the router wire them, press Run and watch the simulated power flow on the canvas — then build logic gates, link chiplets, and take everything with you as a fab-ready GDS and open formats.

Download v0.19.0 View on GitHub

Windows · Linux · macOS — MIT licensed

Meet LunimaThe short introduction
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▶ Run  place → route → simulate Optics · CW @ 1550 nm
A Mach-Zehnder chip builds itself in the Lunima main window: components are placed one by one, the router wires connection after connection, golden DC metal traces reach the probe and bond pads — then the Optics workspace's Run button lights up the simulated power flow on every waveguide.

One design, four views

Workspaces that know what you're doing

Layout, Optics, Logic and System look at the same design. Each brings its own accent colour, its own Run button and the left panel and analysis tabs you need right now — nothing else.

  • Layout — component library, routing tools; Run checks the design.
  • Optics — sources & detectors; Run toggles the live simulation.
  • Logic — gates and starter circuits; Run builds the logic network.
  • System — chiplets and their links, with the loss across each link.
Ctrl+1…4  Layout · Optics · Logic · System Two Chiplets — Edge-Coupler Link
Switching the shipped two-chiplet example through the Layout, Optics, Logic and System workspaces: the accent colour, the Run button, the left panel (library, sources, gates, chiplets) and the analysis tabs change with each workspace.

If you simulate — and then measure

Simulation lives on the canvas

Turn the simulation on once. Every edit after that — a new wire, a moved part, a parameter — re-runs it in the background and repaints the power flow.

  • Live CW power flow — dB and percent on every waveguide, updated as you edit.
  • Transient & Eye / BER — IFFT of the circuit S-parameters, PRBS eye heat maps with Q-factor and BER, CSV export.
  • ONA sweeps & spectra — transmission over wavelength per output pin.
  • FDTD with Meep — recompute a component's S-matrix from its geometry in Docker.
  • Measured data in — load S-matrices from file onto the components you drew.
● Simulation on  live re-run on every edit Phase shifter 0° → 360°
With the simulation on, connecting the missing combiner-to-detector wire lights it up by itself; sweeping the phase shifter's phase through 360 degrees moves the light between the photodetector and the output coupler, every frame a real live re-run.
Eye / BER  PRBS-7 @ 25 Gbps threshold 0.50 | Export CSV
Eye/BER analysis: a PRBS-7 modulated transient folded into an eye-persistence heat map at 25 gigabits per second, with bit rate, pattern and threshold controls.

If you route by hand

Routing that answers to you

The router suggests, you decide. Cut a wire to let another one cross, slide a crossing along its wire — only the pieces that have to move are re-routed.

  • Cut tool — cut any wire, even one coming out of a crossing; a real PDK crossing drops in and the halves keep their geometry.
  • Slide crossings — drag along an axis; Shift frees the drag.
  • Per-connection styles — SBend, Bend, custom radii with in-canvas handles; freeze routes you've tuned.
  • Process-aware — routing honours your process's minimum bend radius.
  • Metal routing & diagonal 45°opt-in — DC traces next to the optical layer, denser layouts.
✂ Cut  then drag the crossing only the perpendicular pieces re-route
Two wires cross through a waveguide crossing. The Cut tool cuts the wire coming out of it, a new crossing drops in and a third wire runs straight through it; then dragging the first crossing along its wire stretches only the horizontal pieces while the two perpendicular pieces re-route.

If you compute with light

From parts to a logic gate

Select a few photonic parts and press Make gate. Lunima groups them, simulates every input combination and proposes the threshold that turns the optical powers into a truth table.

  • Make gate — pin roles, real simulation, suggested threshold and margin in dB.
  • Gate library — save gates and drag them into bigger circuits: adders, latches, RAM, an ALU.
  • Logic network — toggle inputs and watch every gate output live, or step the clock.
Logic  Make gate → NAND Reads NAND in every row
In the Logic workspace the parts of the gate kit are box-selected, Make gate groups them and opens the gate steps, and the simulated truth table with its automatic threshold reads NAND in every row.

If one die isn't enough

Chiplets, linked by light

Put two dies side by side and butt-couple them through edge couplers. Knock one out of alignment and the live simulation shows the link losing light — Design Checks name the offset, one click snaps it back.

  • Dies with their own process — the System workspace lists every chiplet with its process.
  • Link loss you can see — every edge-coupler link carries its loss in dB.
  • Align chiplet — a lateral offset is a design-check finding with a one-click fix.
  • Logic across dies — gate networks follow the light through edge-coupler links.
System  Transmitter ↔ Receiver chiplet 0.00 dB → 16.71 dB → 0.00 dB
Two chiplets butt-coupled through edge couplers in the System workspace: dragging the receiver die off the transmitter's edge coupler raises the link loss to 16.7 dB and dims the output, Design Checks report the lateral offset, and Align chiplet snaps the die back.

If you work with an AI agent

Claude can repair your design

Lunima's agent bridge speaks MCP. An agent such as Claude inspects the open design, tries fixes in a sandbox and applies the one that works — through the same undoable commands you use.

  • Inspect — design summary, components, connections, routing timings, screenshots.
  • Edit — move and delete components, reroute, undo.
  • Repair — cut candidates, crossing slides, segment shifts, sandboxed fix suggestions.
MCP  list_connections → suggest_fixes → move_component 0 of 12 blocked
A terminal-style overlay lists the real MCP tool calls an agent makes on the canvas: list_connections finds the blocked metal trace of a moved probe pad, suggest_fixes tries nudges in a sandbox, move_component moves the pad clear and all 12 connections route.

If you run your own fab

Your PDK is a first-class citizen

Custom PDKs aren't an expert backdoor. Define components in gdsfactory or nazca Python, preview the geometry, compute the S-matrix with Meep — and keep your process data (it's entered per process, never shipped).

  • One editor for everything — code, geometry preview and S-matrix side by side.
  • Fork-on-save — editing a bundled component forks it into your PDK; restore the original any time.
  • Trash, not dread — deleted PDKs and components restore for 30 days.
  • Process editor — layer stack, cross-sections with bend radii the router enforces, your own refractive indices.
Edit  1×2 MMI Splitter — Demo PDK GdsFactory | Meep
The unified component editor: PDK and fabrication-process context, syntax-highlighted gdsfactory Python code, a rendered geometry preview of the 1x2 MMI, and one-click S-matrix computation via Meep FDTD.

If you tape out

Built to tape out

Layouts target real foundry processes from the first component you place — so what leaves the Export menu is a GDS a fab can actually make.

  • Real foundry PDKs, bundled — CornerStone SiN 300 nm and the open SiEPIC EBeam SOI 220 nm, next to the Demo PDK.
  • Calibrated against the cells — the offset editor renders the PDK's actual GDS polygons and verifies every pin.
  • One design, one process — free mixing lives in a Playground the status bar labels not manufacturable.
  • GDS via gdsfactory or nazca — plus SAX, PhotonTorch, Verilog-A and YAML netlists from the same menu.
⇄ 1:1  canvas ↔ exported GDS (gdsfactory) same circuit · same scale · same position
What you draw is what you tape out: the MZI core drawn on the Lunima canvas next to the rendered polygons of the GDS actually exported through gdsfactory — every waveguide, bend and metal trace in the same place.
Export  GDS via gdsfactory · nazca Check-All: all aligned | Δ 0.00 µm
The manufacturing story: the Export flyout over the chip listing the GDS, SAX, PhotonTorch, Verilog-A and netlist back-ends, the PDK calibration editor rendering the SiEPIC grating coupler's actual GDS geometry with its pins aligned, and an all-green Check-All report.

If you don't trust black boxes

Open by design

Every stage has an escape hatch. Your circuit is a graph you can export, your PDK is JSON you can diff, and nothing in the pipeline requires you to stay.

Get Lunima

Download v0.19.0

Free and MIT-licensed. Once installed, Lunima updates itself in place — download, swap, relaunch — on all three platforms.

Windows

x64

Lunima-Setup-0.19.0.msi Lunima-0.19.0-win-x64.zip

Installer, or portable zip — unzip and run.

Linux

x64

Lunima-0.19.0-linux-x64.tar.gz

Extract into its own folder and run.

macOS

Apple Silicon · Intel

Lunima-0.19.0-osx-arm64.dmg Lunima-0.19.0-osx-x64.dmg

Unsigned build — see the first-launch note below.

macOS first launch: xattr -dr com.apple.quarantine /Applications/Lunima.app
All versions: github.com/aignermax/Lunima/releases

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